1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems. In particular, the present invention relates to a method and system that improve the model build and simulation processes in order to allow a designer to easily instrument and monitor a simulation model. More particularly, the present invention relates to generating cross-hierarchical simulation model events within hardware description language simulation models.
2. Description of the Related Art
Verifying the logical correctness of a digital design and debugging the design, if necessary, are important steps in most digital design processes. In a typical automated design process that is supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level description utilizing a hardware description language (HDL), such as VHDL, producing a representation of the various circuit blocks and their interconnections. The ECAD system compiles the design description into a format that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the design prior to developing a circuit layout.
A simulator is typically a software tool that processes a digital representation, or simulation model of a circuit, together with a list of input stimuli representing inputs of the digital system. The simulator generates a numerical representation of the circuit response that may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general-purpose computer or on another piece of electronic apparatus specially designed for simulation. Simulators that run entirely in software on a general-purpose computer are often referred to as “software simulators”. Simulators that are run with the assistance of specially designed electronic apparatus are often referred to as “hardware simulators.”
VHDL is a higher-level language utilized for describing the hardware design of complex devices. The overall circuit design is frequently divided into smaller parts (hereinafter referred to as design entities) that are individually designed, often by different design engineers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design. Another advantage of this approach is that errors in a design entity are easier to detect when that entity is simulated in isolation.
It is often advantageous to generate simulation model events that are a logical combination of other events within a given model. Such events that result from combining at least two other simulation events will hereinafter be referred to as “hierarchical events”. Hierarchical events can provide greater insight into the operation of a digital circuit than would otherwise be possible using individualized event analysis.
It is also often advantageous to describe particularly complex events that span multiple entities and a deep hierarchy in terms of a number of simpler events that may be combined to form a hierarchical event. Hierarchically combining events is much simpler than producing an instrumentation entity on the lowest enclosing hierarchy level for each of the design entities from which the event is generated and then individually connecting all of the signals necessary to produce the overall event.
Hierarchical events are particularly advantageous when the overall simulation event is generated from signals contained within replications of the same design entity. In such a circumstance, a single event can be declared once within the replicated design entity such that the replicated events can be directly combined in a higher-level instrumentation entity to form a hierarchical event. An equivalent non-hierarchical event must be individually generated by individually contacting all of the replicated event instance signals. Moreover, the logic utilized to process the replicated event instance signals must be substantially reproduced to create the overall event.
It can therefore be appreciated that a need exists for an improved data structure for permitting hierarchical processing of simulation model events.